Pipelining changes the granularity of a clock cycle to be per step, instead of per-instruction. This allows multiple instructions to be processed concurrently.
If data needs to be used from a prior operation, a pipeline stall would normally be required to remove the hazard and wait for the desired result (a **read-after-write** data hazard). However, a processor can mitigate this hazard by allowing the stalled instrution to read from the prior instruction's result instead.
If a value is produced in memory access (e.g., loads) that is required in the next instruction's EX. a stall is for the dependent instruction. This can be detected in the ID stage by testing if the current instruction sets the memory read flag and the next instruction accesses the destination register.
A processor **stalls** by disabling the PC and IF/ID write to prevent fetching the next instruction. Additionally, it sets the control in ID/EX to 0 to insert a no-op in the pipeline.
## Memory
### Static RAM (SRAM)
- retains data as long as power is supplied
- compared to DRAM, it is faster but more expensive, so it is used for cache
- To **read**: set word line = 1, turning on transistors, then read the **bit line**'s voltage
- To **write**: set word line = 1, turning on transistors, then drive the **bit line**'s voltage
- DRAM capacitors lose their charge over time so must be periodically **refreshed**
- Roughly 5x slower than SRAM, but cheaper, so it is used for main memory
- To **read**: precharge the bit line to $V_{DD}/2$, then set word line = 1, then sense and amplify the voltage change on the bit line. This also writes back the value.
- To **write**: along the bit line, drive $V_DD$ to charge the capacitor (write a $1$) or $GND$ to discharge (write a $0$).
Each bit cell is placed into a symmetric 2D matrix to avoid linear searching. Assuming each addressing pin can address one byte (8 bits), including one bit to select row or column:
The matrix would store a total of eight times the number of bytes / words, so each edge is the square root of that. To read an address, the memory controller gives the row on the address pins and asserts **row address strobe (RAS)**. After the row is read, the controller gives the column and asserts **column address strobe (CAS)**.
A 16 Mib machine stores 2 MiB, or $1024^2$ bytes. Thus the bits are arranged in a $\sqrt{2\times1024^2\times8}=2^{12}$ by $2^{12}$ matrix, where each row holds $2^9$ 8-bit words.
**Synchronous** DRAM (SDRAM) synchronises commands and data transfers to the bus clock. A row is buffered, then data is transferred in bursts of 2<sup>n</sup> words.
**Double data rate** SDRAM transfers data on the rising and falling edges of the bus clock.
### DRAM performance
!!! definition
- **Latency** is measured by the time from the start of the request to the start of data transfer.
- **Bandwidth** is measured by the volume of data transferred per unit time
**DDR SDRAM** transfers 64 bits per channel at once. A **rank** of memory chips provides the data, and each rank chip is mounted on a **dual inline memory module (DIMM)**. To increase capacity without increasing latency, each rank is subdivided into **banks**.
As a JEDEC standard, chips are named by DDR generation and bandwidth:
$$
\text{PC}\#-bandwidth
$$
!!! example
A **PC3-12800** chip is DDR3 with a bus transfer rate of 12800 MB/s. Or, at 8 B/transfer, a bus clock rate of 1600 MT/s. At 2 transfers/cycle (DDR), it must thus run at 800 MHz.
