From 32685046104fa9ed306dd432faa99dc23eea638a Mon Sep 17 00:00:00 2001 From: eggy Date: Mon, 27 Nov 2023 16:05:19 -0500 Subject: [PATCH] ece240: cry --- docs/2a/ece240.md | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/docs/2a/ece240.md b/docs/2a/ece240.md index 4b754a7..1cbdbd5 100644 --- a/docs/2a/ece240.md +++ b/docs/2a/ece240.md @@ -207,3 +207,17 @@ This is a negative feedback loop that forces a constant $I_D$. With two DC supplies ($-V_{EE}, V_{DD}$), having an $R_G$ results in: $$I_D=\frac{-V_{EE}}{R_S}-\frac{V_{GS}}{R_S}$$ + +## PMOS transistors + +These have current flowing from the source to the drain. It is effectively equal to an NMOS at all points but with its polarity reversed. + +\begin{align*} +\tag{triode}I_D&=k_p\left(|V_{ov}|-\frac 1 2V_{SD}\right)V_{SD} \\ +\tag{saturation}I_D&=\frac 1 2 k_p(V_{SG}-|V_{tp}|)^2 +\end{align*} + +### Frequency dependence + +A **parasitic capacitor** from the gate to the source of an NMOS limits the bandwidth (gain). These represent physical limitations of electrodes. At the output, the current through the capacitor can be neglected. At the input, the current through the capacitor dominates. +