From 53759d52bac8724c806975a95e2914ef19e1cd8e Mon Sep 17 00:00:00 2001
From: eggy <danielchen04@hotmail.ca>
Date: Wed, 8 Feb 2023 17:10:30 -0500
Subject: [PATCH] ece124: add registers

---
 docs/1b/ece124.md | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/docs/1b/ece124.md b/docs/1b/ece124.md
index cabfa91..37b2271 100644
--- a/docs/1b/ece124.md
+++ b/docs/1b/ece124.md
@@ -388,7 +388,18 @@ Because flip-flop outputs only change on an active clock edge, there are **propa
 
 A **timing violation** occurs if these timing parameters are not met, which limits clock cycle frequency.
 
+### Registers
 
+!!! definition
+    - An **n-bit register** stores *n* bits.
+
+A flip-flop is a one-bit register.
+
+A **shift register** is a chain of redstone repeaters, consisting of a chain of flip-flops with each output connected to the next input.
+
+<img src="https://upload.wikimedia.org/wikipedia/commons/4/45/4-Bit_SIPO_Shift_Register.svg" width=300>(Source: Wikimedia Commons)</img>
+
+An **up-counter** increments its binary value on input. A **down-counter** decrements its value. It is **synchronous** if all bits update simultaneously.
 
 ## VHDL