ece106: electric field calcs part 1

too tired for part 2

docs/1b/ece106.md

@@ -192,3 +192,25 @@ The **electric field strength** $\vec E$ is the force per unit *positive* charge
 $$\vec E_p=\lim_{q\to 0}\frac{\vec{F}}{q}$$
 
 Please see [SL Physics 1#Electric potential](/sph3u7/#electric-potential) for more information.
+
+### Electric field calculations
+
+If charge is distributed over a three-dimensional object, integration similar to moment of inertia can be used. Where $dQ$ is an infinitely small point charge at point $P$, $d\vec E$ is the electric field at that point, and $r$ is the vector representing the distance from any arbitrary point:
+
+$$d\vec E = \frac{kdQ}{r^2}\hat r$$
+
+!!! warning
+    As the arbitrary point moves, both the direction and the magnitude of the distance from the desired point $P$ change (both $\hat r$ and $r$).
+
+Generally, if a decomposing the vector into Cartesian forms $d\vec E_x$, $d\vec E_y$, and $d\vec E_z$ is helpful even if it is easily calculated in polar form because of the significantly easier ability to detect symmetry in the shape. Symmetry about the axis allows deductions such as $\int d\vec E_y=0$, which makes calculations easier.
+
+In a **one-dimensional** charge distribution (a line), the charge density is used in a similar way as moment of inertia's surface density:
+
+$$dQ=\rho_\ell d\ell$$
+
+**Two-dimensional** charge distributions are more or less the same, but polar or Cartesian forms of the surface area work depending on the shape.
+
+$$dQ=\rho_s dS$$
+
+!!! example
+    A rod of uniform charge density and length $L$ has a charge density of $p_\ell=\frac{Q}{L}$.

docs/1b/ece124.md

@@ -242,9 +242,9 @@ A **negative logic** transistor uses a NOT bubble to represent that it is closed
 ## Hardware
 
 !!! definition
-    - A **programmable logic gate**
-    - A **programmable logic array**
-    - **Programmable array logic**
+    - A **programmable logic gate** does shit
+    - A **programmable logic array** does more shit
+    - **Programmable array logic** is the shit being done
 
 ### FPGAs