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@@ -357,6 +357,39 @@ A **gated D latch** effectively stores $R$ and $S$ by assuming that they are the
(Source: Wikimedia Commons)
+### Flip-flops
+
+**Edge-triggered flip-flops** only change state on the edge of a clock. A negative-edge D flip flop below changes only at the **falling edge** of the clock and is greated with two gated D latches in series. A positive-edge D flip flop can be created by inverting both enable inputs.
+
+
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+
+The asynchronous operations **clear** and **preset** can be added to force the state of the flip-flop to 0 or 1, respectively. To make them synchronous, the input $D$ can be replaced with $D\text{ and clear}'$. These operations are **active low**.
+
+
(Source: Wikimedia Commons
+
+A **T flip-flop** holds state if $T=0$ or **toggles** state if $T=1$.
+
+
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+
+!!! example
+ 
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+
+A **JK flip-flop** acts as a **D flip-flop** if $J\neq K$ and as a **T flip-flop** if $J=K$.
+
+
(Source: Wikimedia Commons)
+
+### Timing analysis
+
+Because flip-flop outputs only change on an active clock edge, there are **propagation delays** before the state changes completely.
+
+- The **setup time** $t_{su}$ is the waiting time the input must be held stable **before** the active clock edge
+- The **hold time** $t_h$ is the time the input must be held stable **after** the active clock edge
+- The **clock-to-output time** $t_{cq}$ is the time required for the output to stabilise after the active clock edge
+
+A **timing violation** occurs if these timing parameters are not met, which limits clock cycle frequency.
+
+
+
## VHDL
VHDL is a hardware schematic language.