ece124: add state machines

docs/1b/ece124.md

@@ -407,6 +407,61 @@ A **Johnson counter** overflows by connecting the complement of the final output
 
 A **ring counter** has exactly one output bit equal to one, looping when it reaches the end. It is equivalent to a loop of redstone repeaters, if redstone repeaters required input to switch to the next repeater.
 
+## Synchronous sequential circuits
+
+A **synchronous sequential circuit** or **state machine** is created with a combinational circuit and a flip-flop.
+
+A **state diagram** is a directed graph with nodes and arcs. Each node represents a state while arcs represent changes in input/output to other states. A circuit with $n$ inputs has $2^n$ arcs.
+
+!!! example
+    A state diagram for a turnstile.
+    
+    <img src="https://upload.wikimedia.org/wikipedia/commons/9/9e/Turnstile_state_machine_colored.svg" width=300>(Source: Wikimedia Commons)</img>
+
+A **state table** is a simplified state diagram.
+
+!!! example
+    Where $A,B,C$ are states, and $w$ is the input, a Moore machine can be represented as:
+    
+    | state | next state | | output |
+    | --- | --- | --- | --- |
+    | | $w=0$ | $w=1$ | |
+    | A | A | B | 0 |
+    | B | A | C | 0 |
+    | C | A | C | 1 |
+
+To design a state circuit:
+
+1. Create a state diagram, select starting state
+2. Minimise the number of states
+3. Decide the number of state variables
+4. Choose flip-flop types and derive next state logic expressions to control flip-flops
+5. Derive logic expressions
+6. Implement the logic expressions
+
+### Moore machine
+
+A Moore machine changes state **only** on the positive edge of the clock. Its output is true only if the previous two inputs were true.
+
+State variables are usually tracked with flip-flops. These can be done with flip-flops treated as binary indexes for each state or with **one hot state** such that one state is tracked with one flip-flop.
+
+### Mealy machine
+
+A Mealy machine changes state **asynchronously**. Its output is true only if the current and past inputs are true.
+
+| state | $w=0$ | $w=1$ | output |
+| --- | --- | --- | --- |
+| A | A | B | 0 |
+| B | A | B | 1 |
+
+### Minimising state
+
+An **equivalent state** is such that each input has the same output and an equivalent next state. Reducing the number of redundant equivalent states minimises the number of states needed.
+
+1. Group states by outputs
+2. For each state, if not all states transition to the same group, subgroup them such that they do
+3. Repeat as necessary
+
 ## VHDL
 
 VHDL is a hardware schematic language.