diff --git a/docs/2a/ece222.md b/docs/2a/ece222.md
index c8dbda3..3cc1e26 100644
--- a/docs/2a/ece222.md
+++ b/docs/2a/ece222.md
@@ -163,7 +163,7 @@ Each bit cell is placed into a symmetric 2D matrix to avoid linear searching. As
 
 $$\text{\# addr bits} = \log_2(2\times\text{\# bytes})$$
 
-The matrix would store a total of eight times the number of bytes / words, so each edge is the square root of that.
+The matrix would store a total of eight times the number of bytes / words, so each edge is the square root of that. To read an address, the memory controller gives the row on the address pins and asserts **row address strobe (RAS)**. After the row is read, the controller gives the column and asserts **column address strobe (CAS)**.
 
 $$
 \text{\# bits} = 2\times\text{\# bytes}\times\frac{\pu{8 bits}}{\pu{1 word}} \\
@@ -173,3 +173,39 @@ $$
 !!! example
     A 16 Mib machine stores 2 MiB, or $1024^2$ bytes. Thus the bits are arranged in a $\sqrt{2\times1024^2\times8}=2^{12}$ by $2^{12}$ matrix, where each row holds $2^9$ 8-bit words.
 
+### DRAM timing
+
+**Asynchronous** DRAM:
+
+1. Provide row number, assert RAS
+2. Wait
+3. Provide column number, assert CAS
+4. Wait
+5. Transfer data
+
+**Fast page mode** DRAM:
+
+1. Provide row number
+2. Specify multiple column numbers
+3. Transfer multiple data
+
+**Synchronous** DRAM (SDRAM) synchronises commands and data transfers to the bus clock. A row is buffered, then data is transferred in bursts of 2<sup>n</sup> words.
+
+**Double data rate** SDRAM transfers data on the rising and falling edges of the bus clock.
+
+### DRAM performance
+
+!!! definition
+    - **Latency** is measured by the time from the start of the request to the start of data transfer.
+    - **Bandwidth** is measured by the volume of data transferred per unit time
+
+**DDR SDRAM** transfers 64 bits per channel at once. A **rank** of memory chips provides the data, and each rank chip is mounted on a **dual inline memory module (DIMM)**. To increase capacity without increasing latency, each rank is subdivided into **banks**.
+
+As a JEDEC standard, chips are named by DDR generation and bandwidth:
+
+$$
+\text{PC}\#-bandwidth
+$$
+
+!!! example
+    A **PC3-12800** chip is DDR3 with a bus transfer rate of 12800 MB/s. Or, at 8 B/transfer, a bus clock rate of 1600 MT/s. At 2 transfers/cycle (DDR), it must thus run at 800 MHz.