diff --git a/docs/1b/ece124.md b/docs/1b/ece124.md
index c3a142e..86c120e 100644
--- a/docs/1b/ece124.md
+++ b/docs/1b/ece124.md
@@ -332,6 +332,31 @@ A **gated latch** is a basic latch as well as a control input that locks the cur
A **flip-flop** contains two gated latches and a control input. The state is only adjustable during the edges of the control signal, so it can only change up to once per cycle.
+### Asynchronous latches
+
+An **RS-NOR** basic latch has a *set* input that must be *reset* before being set again, with one output representing each state. Setting both to one resets both outputs to zero.
+
+
(Source: Wikimedia Commons)
+
+| $R$ | $S$ | $Q$ | $Q'$ |
+| --- | --- | --- | --- |
+| 0 | 0 | no change | no change |
+| 0 | 1 | 1 | 0 |
+| 1 | 0 | 0 | 1 |
+| 1 | 1 | 0 | 0 |
+
+An **RS-NAND** basic latch operates the same way, and looks practically the same, except shifting to $(1, 1)$ resets both to zero instead, and $(0, 0)$ causes no change.
+
+### Synchronous latches
+
+A **NAND gated latch** only allows changes when the clock control input *clk* is on.
+
+
(Source: Wikimedia Commons)
+
+A **gated D latch** effectively stores $R$ and $S$ by assuming that they are the complement for each other, setting $R$ as $D$ and $S$ as $D'$ or vice versa. This **level-sensitive** latch is commonly used to store past state as there is no change when *clk* is zero.
+
+
(Source: Wikimedia Commons)
+
## VHDL
VHDL is a hardware schematic language.