From e02bd8cc46e90cd7fbf9a0a7497acca9f30333f7 Mon Sep 17 00:00:00 2001 From: eggy Date: Tue, 7 Nov 2023 12:57:16 -0500 Subject: [PATCH] ece222: add pipelining --- docs/2a/ece222.md | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/docs/2a/ece222.md b/docs/2a/ece222.md index b1f108b..5676eec 100644 --- a/docs/2a/ece222.md +++ b/docs/2a/ece222.md @@ -111,3 +111,16 @@ To execute an instruction, the following steps are observed: 5. Writeback (WB) - write results to registers from memory, the ALU, or another register +### Performance + +Each step in the instruction data path has a varying time, so the clock period must be at least as long as the slowest step. + +Performance is usually compared by comparing the execution times of standard benchmarks, such that: + +$$\text{time}=n_{instructions}\times\underbrace{\frac{\text{cycles}}{\text{instruction}}}_\text{CPI}\times\frac{\text{seconds}}{\text{cycle}}$$ + +### Pipelining + +Pipelining changes the granularity of a clock cycle to be per step, instead of per-instruction. This allows multiple instructions to be processed concurrently. + +(Source: Wikimedia Commons)