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ece240: cry

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eggy 2023-11-27 16:05:19 -05:00
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@ -207,3 +207,17 @@ This is a negative feedback loop that forces a constant $I_D$.
With two DC supplies ($-V_{EE}, V_{DD}$), having an $R_G$ results in: With two DC supplies ($-V_{EE}, V_{DD}$), having an $R_G$ results in:
$$I_D=\frac{-V_{EE}}{R_S}-\frac{V_{GS}}{R_S}$$ $$I_D=\frac{-V_{EE}}{R_S}-\frac{V_{GS}}{R_S}$$
## PMOS transistors
These have current flowing from the source to the drain. It is effectively equal to an NMOS at all points but with its polarity reversed.
\begin{align*}
\tag{triode}I_D&=k_p\left(|V_{ov}|-\frac 1 2V_{SD}\right)V_{SD} \\
\tag{saturation}I_D&=\frac 1 2 k_p(V_{SG}-|V_{tp}|)^2
\end{align*}
### Frequency dependence
A **parasitic capacitor** from the gate to the source of an NMOS limits the bandwidth (gain). These represent physical limitations of electrodes. At the output, the current through the capacitor can be neglected. At the input, the current through the capacitor dominates.