eggy/eifueo
1
1
Fork 1
Code Issues 2 Pull Requests Releases Wiki Activity

ece124: add flip flops

Browse Source
This commit is contained in:
eggy 2023-02-08 10:34:24 -05:00
parent ecef4402e5
commit 9651673f72
1 changed files with 33 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

33
docs/1b/ece124.md
View File

@ -357,6 +357,39 @@ A **gated D latch** effectively stores $R$ and $S$ by assuming that they are the
<img src="https://upload.wikimedia.org/wikipedia/commons/c/cb/D-type_Transparent_Latch_%28NOR%29.svg" width=400>(Source: Wikimedia Commons)</img>
### Flip-flops
**Edge-triggered flip-flops** only change state on the edge of a clock. A negative-edge D flip flop below changes only at the **falling edge** of the clock and is greated with two gated D latches in series. A positive-edge D flip flop can be created by inverting both enable inputs.
<img src="https://upload.wikimedia.org/wikipedia/commons/5/52/Negative-edge_triggered_master_slave_D_flip-flop.svg" width=500>(Source: Wikimedia Commons)</img>
The asynchronous operations **clear** and **preset** can be added to force the state of the flip-flop to 0 or 1, respectively. To make them synchronous, the input $D$ can be replaced with $D\text{ and clear}'$. These operations are **active low**.
<img src="https://upload.wikimedia.org/wikipedia/commons/8/8c/D-Type_Flip-flop.svg" width=200>(Source: Wikimedia Commons</img>
A **T flip-flop** holds state if $T=0$ or **toggles** state if $T=1$.
<img src="https://upload.wikimedia.org/wikipedia/commons/a/a9/T-Type_Flip-flop.svg" width=200>(Source: Wikimedia Commons</img>
!!! example
<img src="https://upload.wikimedia.org/wikipedia/commons/3/3b/Dual-edge-triggered-flip-flop-XOR.png" width=500>(Source: Wikimedia Commons)</img>
A **JK flip-flop** acts as a **D flip-flop** if $J\neq K$ and as a **T flip-flop** if $J=K$.
<img src="https://upload.wikimedia.org/wikipedia/commons/3/37/JK_Flip-flop_%28Simple%29_Symbol.svg" width=200>(Source: Wikimedia Commons)</img>
### Timing analysis
Because flip-flop outputs only change on an active clock edge, there are **propagation delays** before the state changes completely.
- The **setup time** $t_{su}$ is the waiting time the input must be held stable **before** the active clock edge
- The **hold time** $t_h$ is the time the input must be held stable **after** the active clock edge
- The **clock-to-output time** $t_{cq}$ is the time required for the output to stabilise after the active clock edge
A **timing violation** occurs if these timing parameters are not met, which limits clock cycle frequency.
## VHDL
VHDL is a hardware schematic language.