108 lines
3.7 KiB
Markdown
108 lines
3.7 KiB
Markdown
# ECE 222: Digital Computers
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## Exceptions
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In ARM, anything that interrupts the normal control flow of a program is an exception.
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- An **interrupt** from an **interrupt request (IRQ)** occurs when a peripheral wants to interrupt the current flow
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- A **fault** indicates a CPU error (e.g., division by zero) and returns to the faulty instruction
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- A **trap** runs the interrupt handler and returns to the next instruction
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Exceptions are handled by running an exception handler then returning to the original line.
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### Vector table
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A vector table is an array of handler addresses. Each index contains a number (a "vector") and a priority.
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### Exception handling
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First, in hardware: If the exception priority is higher than the current operating priority, the exception is immediately handled.
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- the current context is pushed to the stack
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- the operating mode is set to privileged
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- the operating priority is set to the exception priority
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- the program counter is set to the address of the exception (`vector_table[exception_num]`)
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Next, the handler runs, and it should:
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- preserve the any R4-R11 it modifies
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- clear the interrupt request (IRQ)
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- restore R4-R11
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- return with `BX LR`
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Finally, in hardware:
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- the previous context is restored
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- the previous operating priority and mode are restored
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!!! warning
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Interrupts can interrupt other interrupts, if their priority is sufficiently high!
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!!! example
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How to interrupt-driven I/O:
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**Write the ISR:** Assuming that the IRQ bit is cleared if `R0` is read:
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```asm
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ISR PUSH {R4-R11} ; save previous state onto stack
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LDR R3, [R0] ; clear the IRQ by reading from it
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POP {R4-R11} ; restore state
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BX LR ; return to original address
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```
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**Store the interrupt handler in the vector table:** Assuming that the vector number is `22` and the vector table starts 16 addresses after the 0x00:
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```asm
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MOV32 R0, #ISR ; handler address
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MOV R1, #38 * 4 ; offset: (16 + 22) * 4 bytes per address
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STR R1, [R0] ; save address to table
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```
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**Enable interrupt requests:**
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```asm
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MOV32 R0, #ADDRESS_INTERRUPT_ENABLE
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MOV R1, #1
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STR R1, [R0] ; enable interrupts
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```
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## Processor design
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Comparing the **complex instruction set computer** architecture to the **reduced instruction set computer** architecture:
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| Task | CISC | RISC |
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| ---- | ---- | ---- |
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| ALU operands can come from? | registers, memory | registers (load/store) |
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| Addressing mode | complex | simple |
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| Binary size | small | large (~30% larger) |
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| Instruction size | variable | fixed |
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| Pipelining | difficult | simple |
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### Operation encoding
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The **R-format** is used for operations of the form `ADD Rd, Rn, Rm`:
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$$\underbrace{\text{op-code}}_\text{11 b}\ \ \overbrace{\text{Rm}}^\text{5 b}\ \ \underbrace{\text{shift amount}}_\text{6 b}\ \ \overbrace{\text{Rn}}^\text{5 b}\ \ \underbrace{\text{Rd}}_\text{5 b}$$
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The **D-format** is used for operations of the form `LDR Rt, [Rn, #offset]`:
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$$\underbrace{\text{op-code}}_\text{11 b}\ \ \overbrace{\text{offset}}^\text{9 b}\ \ 00\ \ \overbrace{\text{Rn}}^\text{5 b}\ \ \underbrace{\text{Rt}}_\text{5 b}$$
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The **CB-format** is used for operations of the form `CBZ Rt, LABEL`:
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$$\underbrace{\text{op-code}}_\text{8 b}\ \ \overbrace{\text{offset}}^\text{19 b}\ \ \underbrace{\text{Rt}}_\text{5 b}$$
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### Instruction data path
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To execute an instruction, the following steps are observed:
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1. Instruction fetch (IF)
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- fetch the instruction from instruction memory
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- increment the instruction address (`PC += 4`), latchedd into PC register at the end of the CPU cycle
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2. Instruction decode (ID)
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- decode fields like the op-code, offset
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- read recoded registers
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3. Execute (EX)
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- ALU shenanigans
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