ece222: add pipelining

docs/2a/ece222.md

@@ -111,3 +111,16 @@ To execute an instruction, the following steps are observed:
 5. Writeback (WB)
   - write results to registers from memory, the ALU, or another register
 
+### Performance
+
+Each step in the instruction data path has a varying time, so the clock period must be at least as long as the slowest step.
+
+Performance is usually compared by comparing the execution times of standard benchmarks, such that:
+
+$$\text{time}=n_{instructions}\times\underbrace{\frac{\text{cycles}}{\text{instruction}}}_\text{CPI}\times\frac{\text{seconds}}{\text{cycle}}$$
+
+### Pipelining
+
+Pipelining changes the granularity of a clock cycle to be per step, instead of per-instruction. This allows multiple instructions to be processed concurrently.
+
+<img src="https://upload.wikimedia.org/wikipedia/commons/c/cb/Pipeline%2C_4_stage.svg" width=500>(Source: Wikimedia Commons)</img>